完善 CAN DBC 与交付文档

2026-08-09 21:17:09 +08:00
parent 1ac85efc18
commit 04da25e2d1
7 changed files with 267 additions and 84 deletions
@@ -1,77 +0,0 @@
-VERSION "1.0"
-
-NS_ :
-    NS_DESC_
-    CM_
-    BA_DEF_
-    BA_
-    VAL_
-    CAT_DEF_
-    CAT_
-    FILTER
-    BA_DEF_DEF_
-    EV_DATA_
-    ENVVAR_DATA_
-    SGTYPE_
-    SGTYPE_VAL_
-    BA_DEF_SGTYPE_
-    BA_SGTYPE_
-    SIG_TYPE_REF_
-    VAL_TABLE_
-    SIG_GROUP_
-    SIG_VALTYPE_
-    SIGTYPE_VALTYPE_
-    BO_TX_BU_
-    BA_DEF_REL_
-    BA_REL_
-    BA_DEF_DEF_REL_
-    BU_SG_REL_
-    BU_EV_REL_
-    BU_BO_REL_
-    SG_MUL_VAL_
-
-BS_:
-
-BU_: SDC_ACQ_DAC
-
-BO_ 256 SDC_Heartbeat: 8 SDC_ACQ_DAC
- SG_ Board_Identifier : 0|8@1+ (1,0) [0|255] ""  Vector__XXX
- SG_ Protocol_Version : 8|8@1+ (1,0) [0|255] ""  Vector__XXX
- SG_ Heartbeat_Sequence : 16|16@1+ (1,0) [0|65535] ""  Vector__XXX
- SG_ Uptime : 32|32@1+ (0.001,0) [0|4294967.295] "s"  Vector__XXX
-
-BO_ 258 SDC_ADC_Voltage: 2 SDC_ACQ_DAC
- SG_ Input_Voltage : 0|16@1+ (0.001,0) [0|65.535] "V"  Vector__XXX
-
-BO_ 259 SDC_Input_Frequencies: 8 SDC_ACQ_DAC
- SG_ Left_Front_Frequency : 0|16@1+ (1,0) [0|65535] "Hz"  Vector__XXX
- SG_ Left_Rear_Frequency : 16|16@1+ (1,0) [0|65535] "Hz"  Vector__XXX
- SG_ Right_Front_Frequency : 32|16@1+ (1,0) [0|65535] "Hz"  Vector__XXX
- SG_ Right_Rear_Frequency : 48|16@1+ (1,0) [0|65535] "Hz"  Vector__XXX
-
-BO_ 801 SDC_DAC_Set: 3 Vector__XXX
- SG_ DAC_Select : 0|8@1+ (1,0) [1|2] ""  SDC_ACQ_DAC
- SG_ DAC_Command_Voltage : 8|16@1+ (0.001,0) [0|5] "V"  SDC_ACQ_DAC
-
-BO_ 802 SDC_DAC_Ack: 4 SDC_ACQ_DAC
- SG_ DAC_Set_Result : 0|8@1+ (1,0) [0|1] ""  Vector__XXX
- SG_ DAC_Select : 8|8@1+ (1,0) [1|2] ""  Vector__XXX
- SG_ DAC_Output_Voltage : 16|16@1+ (0.001,0) [0|5] "V"  Vector__XXX
-
-BO_ 816 SDC_GPIO_Status: 8 SDC_ACQ_DAC
- SG_ SDC_Input_State : 0|15@1+ (1,0) [0|32767] ""  Vector__XXX
- SG_ SDC_Changed_Mask : 16|15@1+ (1,0) [0|32767] ""  Vector__XXX
- SG_ Timestamp : 32|32@1+ (0.001,0) [0|4294967.295] "s"  Vector__XXX
-
-VAL_ 801 DAC_Select 1 "DAC1" 2 "DAC2" ;
-VAL_ 802 DAC_Set_Result 0 "Failed" 1 "OK" ;
-VAL_ 802 DAC_Select 1 "DAC1" 2 "DAC2" ;
-
-CM_ BO_ 256 "Standard ID 0x100. Sent every 1 s on both CAN1 and CAN2.";
-CM_ BO_ 258 "Standard ID 0x102. Filtered, calibrated voltage before the hardware divider.";
-CM_ BO_ 259 "Standard ID 0x103. Input capture frequency order: PA0, PA2, PA6, PB14.";
-CM_ BO_ 801 "Standard ID 0x321. Accepted on CAN1 and CAN2. Voltage is commanded in mV on-wire.";
-CM_ BO_ 802 "Standard ID 0x322. Broadcast acknowledgement on CAN1 and CAN2.";
-CM_ BO_ 816 "Standard ID 0x330. Sent at startup and whenever PD0-PD14 state changes, on both CAN buses.";
-CM_ SG_ 816 SDC_Input_State "Bit 0 through bit 14 map directly to PD0 through PD14.";
-CM_ SG_ 816 SDC_Changed_Mask "A set bit identifies an input that changed since the preceding GPIO-status frame.";